參數(shù)資料
型號(hào)： SI3225DC0-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 84/112頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3225
已供物品： 板，CD
Si3220/25 Si3200/02
Rev. 1.3
73
Not
Recommended
fo
r N
ew
D
esi
gn
s
3.27. Interrupt Logic
The Dual ProSLIC devices are capable of generating
interrupts for the following events:
Loop current/ring ground detected
Ring trip detected
Ground Key detected
Power alarm
DTMF digit detected
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
RAM address access complete
Receive path modem tone detected
Transmit path modem tone detected
The interface to the interrupt logic consists of six
registers. Four interrupt status registers (IRQ0–IRQ3)
contain 1 bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain 1 bit for each interrupt
function. For interrupt mask registers, the bits are active
high. Refer to the appropriate functional description text
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0–IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-zero,
the INT pin remains asserted.
3.28. SPI Control Interface
The control interface to the Dual ProSLIC devices is a
4-wire SPI bus modeled after microcontroller and serial
peripheral devices. The interface consists of a clock,
SCLK, chip select, CS, serial data input, SDI, and serial
data output, SDO. In addition, the Dual ProSLIC devices
include a serial data through output (SDI_THRU) to
support daisy-chain operation of up to eight devices (up
to sixteen channels). Figure 41 illustrates the daisy-
chain connections. Note that the SDITHRU pin of the
last device in the chain must not be connected to
ground (SDITHRU = 0 indicated GCI mode). The device
operates with both 8-bit and 16-bit SPI controllers.
Each SPI operation consists of a control byte, an
address byte (of which only the seven LSBs are used
internally), and either one or two data bytes depending
on the width of the controller and whether the access is
to an 8-bit register or 16-bit RAM address. Bytes are
always transmitted MSB first. The variations of usage
on this four-wire interface are as follows:
Continuous clocking. During continuous clocking,
the data transfers are controlled by the assertion of
the CS pin. CS must be asserted before the falling
edge of SCLK on which the first bit of data is
expected during a read cycle and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
Clock during transfer only. In this mode, the clock
is cycling only during the actual byte transfers. Each
byte transfer consists of eight clock cycles in a return
to “1” format.
SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tri-stating its output during the
data byte transfer of a read operation.
Soft reset. The SPI state machine resets whenever
CS asserts during an operation on an SCLK cycle
that is not a multiple of eight. This is a mechanism
for the controller to force the state machine to a
known state when the controller and the device are
out of synchronization.
As shown in the application schematics in Figure 12 on
page 26 and Figure 13 on page 27, a pulldown resistor
is required on the SDO pin to ensure proper operation.
A pullup resistor is not allowed on the SDO pin.
相關(guān)PDF資料
PDF描述
SEK220M400ST CAP ALUM 22UF 400V 20% RADIAL
CP2201EK KIT EVAL FOR CP2201 ETH CTRLR
PM1210-820J-RC INDUCTOR 82UH 5% 1210 SMD
H3WWH-6036G IDC CABLE - HPL60H/AE60G/HPL60H
UPS2C471MRD CAP ALUM 470UF 160V 20% RADIAL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI3225DCX-EVB 功能描述:子卡和OEM板 Si3225 Daughter Card RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
Si3225-FQ 功能描述:電信線路管理 IC Dual-Channel SLIC/ codec RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3225-FQR 制造商:Silicon Laboratories Inc 功能描述:
Si3225-G-FQ 功能描述:電信線路管理 IC Dual-Channel SLIC codec RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3225-G-FQR 功能描述:電信線路管理 IC Dual-CH SLIC/codec Ext Ringing Support RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*