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參數(shù)資料
| 型號： | SI3225DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 88/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3225 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
Rev. 1.3
77
Not
Recommended
fo
r N
ew
D
esi
gn
s
operations to register addresses via a 16-bit SPI
controller. These operations require a 4-byte transfer
arranged as two 16-bit words. The absence of CS going
high after the eighth bit of data indicates to the SPI state
machine that eight more SCLK pulses follow to
complete the operation. For a WRITE operation, the last
eight bits are ignored. For a read operation, the 8-bit
data value repeats so that the data is captured during
the last half of a data transfer if required by the
controller.
During register accesses, the CONTROL, ADDRESS,
and DATA are captured in the SPI module. At the
completion of the ADDRESS byte of a READ access,
the contents of the addressed register move into the
data register of the SPI data register. At the completion
of the DATA byte of a WRITE access, the data is
transferred from the SPI to the addressed register.
Figures 47–50 illustrate the various cycles for accessing
RAM addresses. RAM addresses are 16-bit entities;
therefore, the accesses always require four bytes.
During
RAM
address
accesses,
the
CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer
move into the data register in the SPI for shifting out
during the DATA portion of the SPI transfer. This is the
data loaded into the data buffer in response to the
previous RAM address read request. Therefore, there is
a one-deep pipeline nature to RAM address READ
operations. At the completion of the DATA portion of the
READ cycle, the ADDRESS is transferred to the
channel-based address buffer register, and a RAM
address is logged for that channel. The RAMSTAT bit in
each channel is polled to monitor the status of RAM
address accesses that are serviced twice per sample
period at dedicated windows in the DSP algorithm.
A RAM access interrupt in each channel indicates that
the pending RAM access request is serviced. For a
RAM access, the ADDRESS and DATA is transferred
from the SPI registers to the address and data buffers in
the appropriate channel. The RAM WRITE request is
logged. As for READ operations, the status of the
pending request is monitored by either polling the
RAMSTAT bit for the channel or enabling the RAM
access interrupt for the channel. By keeping the
address, data buffers, and RAMSTAT register on a per-
channel
basis,
RAM
address
accesses
can
be
scheduled for both channels without interface.
Figure 45. Register Write Operation via a 16-Bit SPI Port
Figure 46. Register Read Operation via a 16-Bit SPI Port
X X X X X X X X
CS
SCLK
SDI
SDO
CONTROL
ADDRESS
Data [7:0]
Hi - Z
X X X X X X X X
CS
SCLK
SDI
SDO
Data [7:0]
CONTROL
ADDRESS
X X X X X X X X
Data [7:0]
Same byte repeated twice.
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