參數(shù)資料
型號(hào): SI3230MPPQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 105/108頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
96
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in twos-complement format.
Note:
The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but should be written to zeroes.
Table 37. SLIC Control Indirect Registers Summary
Addr. D15
D14
D13
D12
D11
D10
D9
D8D7D6D5D4D3D2D1
D0
28
LCRT[5:0]
29
RPTP[5:0]
30
CML[5:0]
31
CMH[5:0]
32
PPT12[7:0]
33
PPT34[7:0]
34
PPT56[7:0]
35
NCLR[12:0]
36
NRTP[12:0]
37
NQ12[12:0]
38
NQ34[12:0]
39
NQ56[12:0]
40
VCMR[3:0]
41
VMIND[3:0]*
42
43
LCRTL[5:0]
*Note:
Si3230 only.
Table 38. SLIC Control Indirect Registers Description
Addr.
Description
28
Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
29
Ring Trip Threshold.
Ring trip detection threshold during ringing. See "2.4.6. Ring Trip Detection" on page 31.
30
Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
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