參數(shù)資料
型號(hào)： SI3232-G-FQ
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 47/128頁(yè)
文件大?。?/td> 0K
描述： IC SLIC PROG DUAL-CH 64TQFP
標(biāo)準(zhǔn)包裝： 160
功能： 用戶(hù)線(xiàn)路接口概念（SLIC）
接口： ISDN
電路數(shù)： 2
電源電壓： 3.13 V ~ 3.47 V
電流 - 電源： 28mA
功率（瓦特）： 280mW
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
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Si3232
Preliminary Rev. 0.96
25
Not
Recommended
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4.4. Linefeed Calibration
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL register bit. Upon completion of the
calibration cycle, this bit is automatically reset.
It is recommended that a calibration be executed
following system powerup. Upon release of the chip
reset, the device is in the Open state, and calibration
can be initiated. Only one calibration should be
necessary as long as the system remains powered up.
The Dual ProSLIC calibration sequence consists of
SLIC mode calibration, monitor ADC calibration, and
audio path calibration. The calibration bits that are set in
registers CALR1 and CALR2 are executed in order of
MSB to LSB for each sequential register. CALR1, bit 7
starts the calibration sequence. CALR2 calibration bits
should be set before the CALR1 is written. The reserved
bit (bit 6) of CALR1 must always be cleared to 0. The
interrupt bit, bit 7 of IRQ3, will report an error in the
calibration process. The error could include the line
becoming off-hook during the common mode balance
calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration.
The leakage calibrations (CALR1, bits 4–5) can be done
at regular intervals to provide optimal performance over
temperature
variations.
The
TIP/RING
leakage
calibrations can be performed every hour. Invoke these
leakage calibrations, only during on-hook, by setting
CALR1 to 0xB0. The leakage calibration takes 5 ms and
interferes with dc feed and voice transmission during its
process.
4.4.1. Common Mode Calibration
To optimize common mode (longitudinal) balance
performance, it is recommended that the user perform
the following steps when running the common-mode
calibration routine:
1. Write the Register values as shown in Table 15.
These coefficient values select a 600
impedance
synthesis
2. Set Common Mode Balance Interrupt
(IRQEN3 = 0x80)
3. Set CALR2 = 0x01. This enables only the AC
longitudinal balance calibration routine (CALCMBAL)
4. Set CALR2 = 0x80. This begins the calibration
process.
5. Wait for the CALR1 register to clear to 0x0,
indicating the longitudinal balance calibration is
complete (up to 100ms).
6. Ensure that a common mode balance error interrupt
did not occur. Retry calibration if true.
7. Rewrite desired register values that were changed
during this calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration. Note that the channel being calibrated
must be on-hook.
Table 14. Register and RAM Locations used for Loop Monitoring
Parameter
Register/RAM
Mnemonic
Register/
RAM Bits
Measurement Range
LSB Size
Effective
Resolution
Loop Voltage Sense
(VTIP – VRING)
VLOOP
VLOOP[15:0]
0 to 64.07 V
64.07 to 160.173 V
4.907 mV
251 mV
628 mV
TIP Voltage Sense
VTIP
VTIP[15:0]
0 to 64.07 V
64.07 V to 160.173 V
4.907 mV
251 mV
628 mV
RING Voltage Sense
VRING
VRING[15:0]
0 to 64.07 V
64.07 V to 160.173 mA
4.907 mV
251 mV
628 mV
Loop Current Sense
ILOOP
ILOOP[15:0]
0 to 101.09 mA
3.907
A500 A*
Longitudinal Current
Sense
ILONG
ILONG[15:0]
0 to 101.09 mA
3.907
A500 A*
Battery Voltage Sense
VBAT
VBAT[15:0]
0 to 64.07 V
64.07 to 160.173 V
4.907 mV
251 mV
628 mV
*Note: ILOOP and ILONG are calculated values based on measured IQ1–IQ4 currents. The resulting effective resolution is
approximately 500
A.
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