參數(shù)資料
型號(hào)： SI3232-G-FQ
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 55/128頁(yè)
文件大小： 0K
描述： IC SLIC PROG DUAL-CH 64TQFP
標(biāo)準(zhǔn)包裝： 160
功能： 用戶(hù)線(xiàn)路接口概念（SLIC）
接口： ISDN
電路數(shù)： 2
電源電壓： 3.13 V ~ 3.47 V
電流 - 電源： 28mA
功率（瓦特）： 280mW
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
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Si3232
32
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.5.1. Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active or On-
Hook Transmission linefeed states (forward or reverse
polarity). The functional blocks required to implement a
loop closure detector are shown in Figure 14, and the
register set for detecting a loop closure event is
provided in Table 19. The primary input to the system is
the Loop Current Sense value provided by the voltage/
current/power monitoring circuitry and reported in the
ILOOP RAM address. The loop current (ILOOP) is
computed by the ISP using the equations shown below.
Refer to Figure 11 on page 26 for the discrete bipolar
transistor references used in the equation below (Q1,
Q2,
Q5
and
Q6
–
note
that
the
Si3200
has
corresponding MOS transistors). The same ILOOP
equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device. The following equation is
conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.
If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and IQ1 is forced to zero in the
FORWARD-ACTIVE and TIP-OPEN states, or IQ2 is
forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
allowed to contribute normally to the ILOOP value.
The conditioning due to the CMH bit (LCRRTP Register)
and LFS field (LINEFEED Register) states can be
summarized as follows:
IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))
The output of the Input Signal Processor is the input to a
programmable digital low-pass filter, which can be used
to remove unwanted ac signal components before
threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location.
LCRLPF = [(2
f x 4096)/800] x 23
Where f is the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled
by
programming
a
second
threshold,
LCRONHK, to detect the loop going to an OPEN or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop-closure debounce
interval, LCRDBI. There is also a loop-closure mask
interval, LCRMASK, that is used to mask transitions
caused when an internal ringing burst (no dc offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit will be
set to indicate that a valid loop closure has occurred.
Table 18. 3-Battery Switching Components
Component
Value
Comments
D1
200 V, 200 mA
IN4003 or similar
Q1
100 V PNP
CXT5401 or similar
Q2
100 V NPN
CXT5551 or similar
R101
1/10 W, ±5%
2.4 k
for V
DD =3.3 V
3.9 k
for V
DD =5 V
R102
10 k
, 1/10 W, ±5%
R103
402 k
, 1/10 W, ±1%
I
loop
I
Q1
I
Q6
–
I
Q5
I
Q2 in TIP-OPEN or RING-OPEN
I
Q1
I
Q6
–
I
Q5
I
Q2
–
+
2
---------------------------------------------------- in all other states
=
–
+
=
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