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參數(shù)資料
| 型號： | SI4123-D-GT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER RF1/IF 24TSSOP |
| 標準包裝： | 62 |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 336-1175 |
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Si4133
16
Rev. 1.61
3. Functional Description
The Si4133 is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for wireless
communications applications. This integrated circuit
(IC), with minimal external components, completes the
frequency
synthesis
function
necessary
for
RF
communications systems.
The Si4133 has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133
suitable
for
demanding
wireless
communications applications. Phase detectors, loop
filters, and reference and output frequency dividers are
integrated. The IC is programmed with a three-wire
serial interface.
Two PLLs are provided for dual-band RF synthesis.
These RF PLLs are multiplexed so that only one PLL is
active at a time, as determined by the setting of an
internal register. The active PLL is the last one to be
written. The center frequency of the VCO in each PLL is
set by the value of an external inductance. Inaccuracies
in these inductances are compensated for by the self-
tuning algorithm. The algorithm is run after powerup or
after a change in the programmed output frequency.
Each RF PLL, when active, can adjust the RF output
frequency by ±5% of its VCO’s center frequency.
Because the two VCOs can be set to have widely
separated center frequencies, the RF output can be
programmed to service two widely separated frequency
bands by programming the corresponding N-Divider.
One RF VCO is optimized to have its center frequency
set between 947 MHz and 1.72 GHz, while the second
RF VCO is optimized to have its center frequency set
between 789 MHz and 1.429 GHz.
One PLL is provided for IF frequency synthesis. The
center frequency of this circuit’s VCO is set by the
connection of an external inductance. The PLL can
adjust the IF output frequency by ±5% of the VCO
center frequency. Inaccuracies in the value of the
external inductance are compensated for by the
Si4133’s
proprietary
self-tuning
algorithm.
This
algorithm is initiated each time the PLL is powered-up
(by either the PWDN pin or by software) and/or each
time a new output frequency is programmed.
The IF VCO can have its center frequency set as low as
526 MHz and as high as 952 MHz. An IF output divider
divides down the IF output frequencies, if needed. The
divider is programmable and is capable of dividing by 1,
2, 4, or 8.
The unique PLL architecture used in the Si4133
produces settling (lock) times that are comparable in
speed to fractional-N architectures without the high
phase noise or spurious modulation effects often
associated with those designs.
3.1. Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4133 is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SEN is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN into the internal data register
addressed in the address field. The serial interface is
disabled when SEN is high.
Table 12 on page 21 summarizes the data register
functions and addresses. The internal shift register
ignores leading bits before the 22 required bits.
3.2. Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% of the center frequencies of their VCOs. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances are acceptable. The Si4133 compensates
for inaccuracies in each inductance by executing a self-
tuning algorithm after PLL powerup or after a change in
the programmed output frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package must be
considered when determining the correct external
inductance. The total inductance (LTOT) presented to
each VCO is the sum of the external inductance (LEXT)
and the package inductance (LPKG). Each VCO has a
nominal capacitance (CNOM) in parallel with the total
inductance, and the center frequency is as follows:
or
VCO.
f
CEN
1
2
L
TOT
C
NOM
-----------------------------------------------
=
f
CEN
1
2
L
PKG
L
EXT
+
C
NOM
------------------------------------------------------------------------
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI4123-D-GTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Single-Band RF Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI4123-EVB | 功能描述:射頻開發(fā)工具 Single-Band RF Synth (RF1/IF) Eval TSSOP RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
| SI4123G | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| SI4123G-BM | 制造商:Silicon Laboratories Inc 功能描述: |
| SI4123G-BMR | 功能描述:鎖相環(huán) - PLL CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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