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參數(shù)資料
| 型號： | SI4123-D-GT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER RF1/IF 24TSSOP |
| 標準包裝： | 62 |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 336-1175 |
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Si4133
Rev. 1.61
17
Figure 15. External Inductance Connection
As a design example, consider that the goal is to
synthesize frequencies in a 25 MHz band between
1120 and 1145 MHz using the Si4133-GT. The center
frequency should be defined as midway between the
two extremes, or 1132.5 MHz. The PLL can adjust the
VCO output frequency ±5% of the center frequency, or
±56.6 MHz of 1132.5 MHz (i.e., from approximately
1076 to 1189 MHz). The RF2 VCO has a CNOM of
4.8 pF. A 4.1 nH inductance in parallel with this
capacitance yields the required center frequency. An
external inductance of 1.8 nH should be connected
between RFLC and RFLD as shown in Figure 15. This,
in addition to 2.3 nH of package inductance, presents
the
correct
total
inductance
to
the
VCO.
In
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4133 corrects for the
variation with the self-tuning algorithm.
For more information on designing the external trace
inductors, refer to Application Note 31: Inductor Design
for the Si41xx Synthesizer Family.
3.3. Extended Frequency Operation
The Si4133 may operate at an extended frequency
range of 1850 MHz to 2050 MHz by connecting the
RFLA and RFLB pins directly. For information on
configuring
the
Si4133
for
extended
frequency
operation, refer to Application Note 41: Extended
Frequency Operation of Silicon Laboratories Frequency
Synthesizers.
3.4. Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately after
powerup of a PLL or, if the PLL is already powered, after
a change in its programmed output frequency. This
algorithm attempts to tune the VCO so that its free-
running frequency is near the required output frequency.
In
doing
so,
the
algorithm
compensates
for
manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It also
reduces the frequency error for which the PLL must
correct to get the precise required output frequency. The
self-tuning algorithm leaves the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL completes frequency locking,
eliminating any remaining frequency error. From then
on, it maintains frequency-lock, compensating for
effects of temperature and supply voltage variations.
The Si4133’s self-tuning algorithm compensates for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur
after
self-tuning
is
limited.
For
external
inductances
with
temperature
coefficients
approximately ±150 ppm/oC, the PLL can maintain lock
for changes in temperature of approximately ±30 oC.
Applications where the PLL is regularly powered down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it might be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
run out of locking capability. See “3.10. Auxiliary Output
Table 6. Si4133-GT VCO Characteristics
VCO fCEN Range
(MHz)
CNOM
(pF)
LPKG
(nH)
LEXT Range
(nH)
Min
Max
Min
Max
RF1
947
1720
4.3
2.0
0.0
4.6
RF2
789
1429
4.8
2.3
0.3
6.2
IF
526
952
6.5
2.1
2.2
12.0
Table 7. Si4133-GM VCO Characteristics
VCO fCEN Range
(MHz)
CNOM
(pF)
LPKG
(nH)
LEXT Range
(nH)
Min
Max
Min
Max
RF1
947
1720
4.3
1.5
0.5
5.1
RF2
789
1429
4.8
1.5
1.1
7.0
IF
526
952
6.5
1.6
2.7
12.5
L
PKG
2
L
PKG
2
L
EXT
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PDF描述 |
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| SI4113-D-GT | IC SYNTHESIZER RF1/RF2 24TSSOP |
| SI4122-D-GM | IC SYNTH RF2/IF SNGL-BAND 28MLP |
| SI4113-D-GM | IC SYNTHESIZER RF-ONLY 28MLP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI4123-D-GTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Single-Band RF Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI4123-EVB | 功能描述:射頻開發(fā)工具 Single-Band RF Synth (RF1/IF) Eval TSSOP RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
| SI4123G | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| SI4123G-BM | 制造商:Silicon Laboratories Inc 功能描述: |
| SI4123G-BMR | 功能描述:鎖相環(huán) - PLL CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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