CKNDC Whichever is smaller (i.e., the 40% / 6" />
參數(shù)資料
型號(hào): SI5319-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 2/50頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION SI5319
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘乘法器
嵌入式:
已用 IC / 零件: SI5319
主要屬性: 1 輸入,1 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5319
10
Rev. 1.0
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high-frequency
clocks)
40
60
%
2—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUT Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOF
N1
6
0.002
945
MHz
N1 = 5
970
1134
MHz
N1 = 4
1.213
1.4
GHz
Maximum Output
Frequency in CMOS
Format
CKOF
212.5
MHz
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
—230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =1.71
CLOAD =5 pF
——
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =2.97
CLOAD =5 pF
——
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100
Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
——
+/-40
ps
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
1—
s
Reset to Microproces-
sor Access Ready
tREADY
——
10
ms
Input Capacitance
Cin
——
3
pF
Table 4. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
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