參數(shù)資料
型號(hào): SI5319-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/50頁
文件大小: 0K
描述: BOARD EVALUATION SI5319
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘乘法器
嵌入式:
已用 IC / 零件: SI5319
主要屬性: 1 輸入,1 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5319
14
Rev. 1.0
2. Typical Phase Noise Plots
The following typical phase noise plot was taken using a Rohde and Schwarz SML03 RF Generator as the clock
input source to the Si5326. The Agilent model E5052B was used for the phase noise measurement. For this
measurement, the Si5319 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled
differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is
below the loop BW is caused by the jitter at the input clock. The loop BW was 120 Hz.
2.1. Example: SONET OC-192
Figure 3. Typical Phase Noise Plot
T
Jitter Band
Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz
250 fs
SONET_OC192_A, 20 kHz to 80 MHz
274 fs
SONET_OC192_B, 4 to 80 MHz
166 fs
SONET_OC192_C, 50 kHz to 80 MHz
267 fs
Brick Wall, 800 Hz to 80 MHz
274 fs
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