CKOTRF Output not configured for CMOS" />
參數(shù)資料
型號(hào): SI5324B-C-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-808MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 808MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5324
10
Rev. 1.1
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
—230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =1.71
CLOAD =5 pF
——
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =2.97
CLOAD =5 pF
——
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100
Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
——
+/-40
ps
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
1s
Reset to Microproces-
sor Access Ready
tREADY
10
ms
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD =20pf
—25
ns
LOSn Trigger Window
LOSTRIG
From last CKINn
to
Internal detection of LOSn
N3 ≠ 1
4.5 x N3
TCKIN
Time to Clear LOL after
LOS Cleared
tCLRLOL
LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—10
ms
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT
setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency
Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding
the lock time of your frequency plan.
3. LOCKT = 3.3 ms
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