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參數(shù)資料
型號(hào): SI5324B-C-GMR
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 60/72頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-808MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 808MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5324
Rev. 1.1
63
26
A2_SS
ILVCMOS
Serial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27
SDI
I
LVCMOS
Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
29
28
CKOUT1–
CKOUT1+
OMulti
Output Clock 1.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by
SFOUT1_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
34
35
CKOUT2–
CKOUT2+
OMulti
Output Clock 2.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by
SFOUT2_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
36
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the Si5324.
0=I2C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Pin #
Pin Name I/O Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
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