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參數(shù)資料
| 型號： | SI5338A-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN QUAD 700MHZ 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | MultiSynth™ |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | CML，HCSL，HSCL，LVDS，LVPECL，晶體 |
| 輸出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 628 (CN2011-ZH PDF) |
| 配用： | 336-1747-ND - KIT PROG FIELD SI5338/4/0 336-1556-ND - BOARD EVALUATION SI5338 |
| 其它名稱： | 336-1553-5 |
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Si5338
20
Rev. 1.3
3.4. Output Stage
The output stage consists of output selectors, output
dividers, and programmable output drivers as shown in
Figure 7. Output Stage
The output selectors select the clock source for the
output drivers. By default, each output driver is
connected to its own MultiSynth block (e.g. MS0 to
CLK0, MS1 to CLK1, etc), but other combinations are
possible by reconfiguring the device. The PLL can be
bypassed by connecting the input stage signals (osc,
ref, refdiv, fb, or fbdiv) directly to the output divider.
Bypassing an input directly to an output will not allow
phase alignment of that output to other outputs. Each of
the output drivers can also connect to the first
MultiSynth block (MS0) enabling a fan-out function. This
allows the Si5338 to act as a clock generator, a fanout
buffer, or a combination of both in the same package.
The output dividers (R0, R1, R2, R3) allow another
stage of clock division.These dividers are configurable
as divide by 1 (default), 2, 4, 8, 16, or 32. When an Rn
does not equal 1, the phase alignment function for that
output will not work.
The output drivers are configurable to support common
signal formats, such as LVPECL, LVDS, HCSL, CMOS,
HSTL, and SSTL. Separate output supply pins (VDDOn)
are provided for each output buffer.
The voltage on these supply pins can be 3.3, 2.5, 1.8, or
1.5 V as needed for the possible output formats.
Additionally, the outputs can be configured to stop high,
low, or tri-state when the PLL has lost lock. If the Si5338
is used in a zero delay mode, the output that is fed back
must be set for always on, which will override any
output disable signal.
Each of the outputs can also be enabled or disabled
through the I2C port. A single pin to enable/disable all
outputs is available in the Si5338K/L/M.
3.5. Configuring the Si5338
The Si5338 is a highly-flexible clock generator that is
entirely configurable through its I2C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 8. The NVM is a
one-time programmable memory (OTP), which can
store a custom user configuration at power-up. This is a
useful feature for applications that need a clock present
at power-up (e.g., for providing a clock to a processor).
Figure 8. Si5338 Memory Configuration
During a power cycle or a power-on reset (POR), the
contents of the NVM are copied into random access
memory (RAM), which sets the device configuration that
will be used during operation. Any changes to the
device configuration after power-up are made by
reading and writing to registers in the RAM space
through the I2C interface. ClockBuilder Desktop (see
can be used to easily configure register map files that
can be written into RAM (see “3.5.2. Creating a New
Configuration for RAM” for details). Alternatively, the
register map file can be created manually with the help
of the equations in the Si5338 Reference Manual.
Two versions of the Si5338 are available. First,
standard, non-customized Si5338 devices are available
in which the RAM can be configured in-circuit via I2C
(example part number Si5338C-A-GM). Alternatively,
standard Si5338 devices can be field-programmed
using the Si5338/56-PROG-EVB field programmer.
Second, custom factory-programmed Si5338 devices
are available that include a user-specified startup
frequency
configuration
(example
part
number
Si5338C-Axxxxx-GM). See "12. Ordering Information"
on page 41 for details.
CLK0A
VDDO1
VDDO2
VDDO3
VDDO0
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷R1
÷R0
÷R2
÷R3
Output
Stage
F
rom
Sy
nt
h
e
s
is
St
ag
e
or
Inpu
t
S
ta
g
e
Power-Up/POR
I
2C
RAM
NVM
(OTP)
Default
Config
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338A-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-program Clk gen 0.16 - 710 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338A-B00302-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338A-B00302-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338A-B00419-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338A-B01206-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
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