DJ Output MultiSynth operated in fractional mode7 —3 15 ps pk-p" />
參數(shù)資料
型號(hào)： SI5338A-A-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 6/44頁(yè)
文件大?。?/td> 0K
描述： IC CLK GEN QUAD 700MHZ 24-QFN
標(biāo)準(zhǔn)包裝： 490
系列： MultiSynth™
類(lèi)型： 時(shí)鐘發(fā)生器
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 700MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 628 (CN2011-ZH PDF)
配用： 336-1747-ND - KIT PROG FIELD SI5338/4/0
336-1556-ND - BOARD EVALUATION SI5338
其它名稱(chēng)： 336-1553-5
Si5338
14
Rev. 1.3
Deterministic Jitter
DJ
Output MultiSynth
operated in fractional
—3
15
ps pk-pk
Output MultiSynth
operated in integer
—2
10
ps pk-pk
Total Jitter
(12kHz–20MHz)
TJ =DJ+14xRJ
(See Note 9)
Output MultiSynth
operated in fractional
—
13
36
ps pk-pk
Output MultiSynth
operated in integer
—
12
20
ps pk-pk
Table 13. itter Specifications, Clock Buffer Mode (PLL Bypass)*
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Additive Phase Jitter
(12kHz–20MHz)
tRPHASE
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
—
0.165
—
ps RMS
Additive Phase Jitter
(50kHz–80MHz)
tRPHASEWB
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
—
0.225
—
ps RMS
*Note: All outputs are in Clock Buffer mode (PLL Bypass).
Table 12. Jitter Specifications1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
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參數(shù)描述
SI5338A-A-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-program Clk gen 0.16 - 710 MHz RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5338A-B00302-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
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