參數(shù)資料
型號(hào): SI5365/66-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 26/28頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5365/66
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
已用 IC / 零件: SI5365,SI5366
已供物品: 板,線纜,CD,文檔
Si5365
Rev. 0.5
7
Figure 1. Differential Voltage Characteristics
Figure 2. Rise/Fall Time Characteristics
LVCMOS Output Pins
Output Voltage Low
VOL
IO = 2 mA
VDD =1.71V
——
0.4
V
Output Voltage Low
IO = 2 mA
VDD =2.97V
——
0.4
V
Output Voltage High
VOH
IO = –2 mA
VDD =1.71V
VDD
0.4
——
V
Output Voltage High
IO = –2 mA
VDD =2.97V
VDD
0.4
——
V
Disabled Leakage
Current
IOZ
RSTb = 0
–100
100
A
Table 1. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD
≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
V
ISE , VOSE
V
ID,VOD
Differential I/Os
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
V
ICM , VOCM
t
F
t
R
80%
20%
CKIN, CKOUT
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