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參數(shù)資料
型號: SI5365/66-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 3/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5365/66
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5365,SI5366
已供物品: 板,線纜,CD,文檔
Si5365
Rev. 0.5
11
Figure 3. Typical Phase Noise Plot
Table 5. Absolute Maximum Limits
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.8
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
CKINn Voltage Level Limits
CKNVIN
0 to VDD
V
XA/XB Voltage Level Limits
XAVIN
0 to 1.2
V
Operating Junction Temperature
TJCT
–55 to 150
C
Storage Temperature Range
TSTG
–55 to 150
C
ESD HBM Tolerance (100 pF, 1.5 k
); All pins except
CKIN+/CKIN–
2kV
ESD MM Tolerance; All pins except CKIN+/CKIN–
150
V
ESD HBM Tolerance (100 pF, 1.5 k
); CKIN+/CKIN–
700
V
ESD MM Tolerance; CKIN+/CKIN–
100
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Jitter Bandwidth
RMS Jitter (fs)
OC-48, 12 kHz to 20 MHz
374
OC-192, 20 kHz to 80 MHz
388
OC-192, 4 MHz to 80 MHz
181
OC-192, 50 kHz to 80 MHz
377
Broadband, 800 Hz to 80 MHz
420
622 MHz In, 622 MHz Out BW=877 kHz
-170
-150
-130
-110
-90
-70
-50
1000
10000
100000
1000000
10000000 100000000
Offset Frequency (Hz)
P
h
ase
N
o
ise
(d
B
c
/H
z
)
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SI5365-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
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SI5365-EVB 制造商:Silicon Laboratories Inc 功能描述: