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參數(shù)資料
| 型號： | SI5365/66-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR SI5365/66 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | SI5365，SI5366 |
| 已供物品： | 板，線纜，CD，文檔 |
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Si5365
Rev. 0.5
13
3. Functional Description
The Si5365 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, SDH STM-16/STM-64, Ethernet, and
Fibre Channel, in which the application requires clock
multiplication without jitter attenuation. The Si5365
accepts four clock inputs ranging from 19.44 to
707 MHz and generates five frequency-multiplied clock
outputs ranging from 19.44 to 1050 MHz. By default the
four clock inputs are at the same frequency and the five
clock outputs are at the same frequency. Two of the
output clocks can be divided down further to generate
an integer sub-multiple frequency. The input clock
frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre
Channel frequencies. In addition to providing clock
multiplication in SONET and datacom applications, the
Si5365
supports
SONET-to-datacom
frequency
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5365 frequency translations. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
The Si5365 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5365 PLL loop bandwidth is
digitally programmable via the BWSEL[1:0] pins and
supports a range from 150 kHz to 1.3 MHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5365 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects a missing
clock.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5365 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize
power
consumption.
For
system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
3.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5365. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5365-B-GQ | 功能描述:時鐘合成器/抖動清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 5 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5365-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5365-C-GQ | 功能描述:時鐘合成器/抖動清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 5 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5365-C-GQR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Pin-Progrm Precision Clk Xplier 4In/5Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
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