
Si5366
Rev. 1.0
9
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XARIN
RATE[1:0] = LM, MH,
ac-coupled
—12
—
k
Input Voltage Swing
XAVPP
RATE[1:0] = LM, MH,
ac-coupled
0.5
—
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XBVPP
RATE[1:0] = LM, MH
0.5
—
2.4
VPP
CKINn Input Pins
Input Frequency
CKNF
.008
—
707.35
MHz
CKIN3 and CKIN4
used as FSYNC pins
CKNF
—8
—
kHz
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
40
—
60
%
2—
—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOF
0.008
—
1050
MHz
Maximum Output
Frequency in CMOS
Format
CKOF
—
212.5
MHz
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
—230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =1.71
CLOAD =5 pF
——
8
ns
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.