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參數(shù)資料
| 型號： | SI5366-C-GQR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULTIPLIER PREC 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時鐘放大器，振動衰減器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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Si5366
16
Rev. 1.0
3. Functional Description
The Si5366 is a jitter-attenuating precision clock
multiplier
for
high-speed
communication
systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5366 accepts four clock inputs ranging
from 8 kHz to 707 MHz and generates five frequency-
multiplied
clock
outputs
ranging
from
8 kHz
to
1050 MHz. By default the four clock inputs are at the
same frequency and the five clock outputs are at the
same frequency. Two of the output clocks can be
divided down further to generate an integer sub-multiple
frequency. Optionally, the fifth clock output can be
configured
as
a
8 kHz
SONET/SDH
frame
synchronization output that is phase aligned with one of
the high-speed output clocks. The input clock frequency
and clock multiplication ratio are selectable from a table
of popular SONET, Ethernet, and Fibre Channel
frequencies. In addition to providing clock multiplication
in SONET and datacom applications, the Si5366
supports SONET-to-datacom frequency translations.
Silicon Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to look up valid Si5366
frequency translations. This utility can be downloaded
from
http://www.silabs.com/timing
(click
on
Documentation).
The Si5366 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5366
PLL loop bandwidth is selectable via the BWSEL[1:0]
pins and supports a range from 60 Hz to 8.4 kHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5366 supports hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (<200 ps typ). Manual and automatic revertive
and non-revertive input clock switching options are
available via the AUTOSEL input pin. The Si5366
monitors the four input clocks for loss-of-signal and
provides a LOS alarm when it detects missing pulses on
any of the four input clocks. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. If a
potential phase cycle slip is detected, the LOL output is
set high. The Si5366 monitors the frequency of CKIN1,
CKIN3, and CKIN4 with respect to a reference
frequency applied to CKIN2, and generates a frequency
offset alarm (FOS) if the threshold is exceeded.
This FOS feature is available for SONET applications in
which both the monitored frequency on CKIN1, CKIN3,
and CKIN4 and the reference frequency are integer
multiples of 19.44 MHz. Both Stratum 3/3E and SONET
Minimum Clock (SMC) FOS thresholds are supported.
The Si5366 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL is locked to an input frequency
that existed a fixed amount of time before the error
event occurred, eliminating the effects of phase and
frequency
transients
that
may
occur
immediately
preceding digital hold.
The Si5366 has five differential clock outputs. The
signal format of the clock outputs is selectable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
3.1. External Reference
An
external,
high
quality
clock
or
a
low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within
the
DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal. Specific recommendations
may be found in the Family Reference Manual.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold, will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
3.2. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5366. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5366-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5367 | 制造商:SILABS 制造商全稱:SILABS 功能描述:レP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
| Si5367/68-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5367/Si5368 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| Si5367A-B-GQ | 功能描述:時鐘合成器/抖動清除器 uP-PROGRAMMABE CLK MULT 10 MHZ-1.4 GHZ RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5367A-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
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