I
參數(shù)資料
型號: SI5368A-C-GQ
廠商: Silicon Laboratories Inc
文件頁數(shù): 83/92頁
文件大?。?/td> 0K
描述: IC CLK MULTIPLIER ATTEN 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSPLL®
類型: 時鐘放大器,振動衰減器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.42GHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Si5368
84
Rev. 1.0
60
SCL
I
LVCMOS
Serial Clock.
This pin functions as the serial port clock input for both SPI and
I2C modes.
This pin has a weak pull-down.
61
SDA_SDO
I/O
LVCMOS
Serial Data.
In I2C microprocessor control mode (CMODE = 0), this pin func-
tions as the bidirectional serial data port. In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
68
69
A0
A1
ILVCMOS
Serial Port Address.
In I2C microprocessor control mode (CMODE = 0), these pins
function as hardware controlled address bits. The I2C address
is 1101 [A2] [A1] [A0]. In SPI microprocessor control mode
(CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
70
A2_SS
ILVCMOS
Serial Port Address/Slave Select.
In I2C microprocessor control mode (CMODE = 0), this pin func-
tions as a hardware controlled address bit [A2].
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
71
SDI
I
LVCMOS
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
In I2C microprocessor control mode (CMODE = 0), this pin is
ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
OMULTI
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
82
83
CKOUT1–
CKOUT1+
OMULTI
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
87
88
FS_OUT–
FS_OUT+
OMULTI
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
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