Figure 4. Si5368 Typical Application Circuit (I2
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� SI5368C-C-GQ
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 10/92闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CLK MULTIPLIER ATTEN 100TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� DSPLL®
椤炲瀷锛� 鏅傞悩鏀惧ぇ鍣�锛屾尟鍕曡“娓涘櫒
PLL锛� 鏄�
杓稿叆锛� 鏅傞悩
杓稿嚭锛� CML锛孋MOS锛孡VDS锛孡VPECL
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 4:5
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鏄�
闋荤巼 - 鏈€澶э細 346MHz
闄ゆ硶鍣�/涔樻硶鍣細 鐒�/鏄�
闆绘簮闆诲锛� 1.71 V ~ 3.63 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
鍖呰锛� 鎵樼洡
Si5368
18
Rev. 1.0
3. Typical Application Circuits
Figure 4. Si5368 Typical Application Circuit (I2C Control Mode)
Si5368
CKIN1+
CKIN1鈥�
INT_ALM
CnB
LOL
RST
CKOUT1+
CKOUT1鈥�
VD
D
GN
D
Ferrite
Bead
System
Power
Supply
C10
C1鈥�9
Input
Clock
Sources*
Reset
Interrupt/Alarm Output
Indicator
CKINn Invalid Indicator
(n = 1 to 3)
PLL Loss of Lock
Indicator
Clock
Outputs
CMODE
Control Mode (L)
CKOUT4+
CKOUT4鈥�
FS_OUT+
FS_OUT鈥�
CKIN4+
CKIN4鈥�
Assumes differential LVPECL termination (3.3 V) on clock inputs.
*Note:
Serial Data
Serial Clock
SDA
SCL
I
2C
Interface
Serial Port
Address
A[2:0]
0.1 F
1 F
0.1 F
100
0.1 F
+
鈥�
0.1 F
100
0.1 F
+
鈥�
0.1 F
100
0.1 F
+
鈥�
130
130
82
82
VDD = 3.3 V
130
130
82
82
VDD = 3.3 V
XA
XB
Crystal
114.285 MHz
XA
XB
Ext. Refclk
0.1 F
Option 1:
Option 2:
0.1 F
RATE[1:0]
Rate
INC
DEC
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
SI5368C-C-GQR 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� Precision Clk Xplier Jitter Attn 4In/5Out RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
SI5368-EVB 鍒堕€犲晢:Silicon Laboratories Inc 鍔熻兘鎻忚堪:
Si5369A-C-GQ 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� LW LOOP BW AR CLK MULT/JITTER 4IN 5OUT RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
SI5369A-C-GQR 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� Lo Loop BW Clk Multi Jitter Attn 4In/5Out RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
Si5369B-C-GQ 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� LW LOOP BW AR CLK MULT/JITTER 4IN 5OUT RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56