- 鎮ㄧ従鍦ㄧ殑浣嶇疆锛�璨疯常IC缍� > PDF鐩寗8952 > SI5368C-C-GQ (Silicon Laboratories Inc)IC CLK MULTIPLIER ATTEN 100TQFP PDF璩囨枡涓嬭級
鍙冩暩璩囨枡
| 鍨嬭櫉锛� | SI5368C-C-GQ |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩锛� | 84/92闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CLK MULTIPLIER ATTEN 100TQFP |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | DSPLL® |
| 椤炲瀷锛� | 鏅傞悩鏀惧ぇ鍣�锛屾尟鍕曡“娓涘櫒 |
| PLL锛� | 鏄� |
| 杓稿叆锛� | 鏅傞悩 |
| 杓稿嚭锛� | CML锛孋MOS锛孡VDS锛孡VPECL |
| 闆昏矾鏁革細 | 1 |
| 姣旂巼 - 杓稿叆:杓稿嚭锛� | 4:5 |
| 宸垎 - 杓稿叆:杓稿嚭锛� | 鏄�/鏄� |
| 闋荤巼 - 鏈€澶э細 | 346MHz |
| 闄ゆ硶鍣�/涔樻硶鍣細 | 鐒�/鏄� |
| 闆绘簮闆诲锛� | 1.71 V ~ 3.63 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 100-TQFP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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Si5368
Rev. 1.0
85
90
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the device.
0=I2C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
92
93
CKOUT2+
CKOUT2鈥�
OMULTI
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
97
98
CKOUT4鈥�
CKOUT4+
OMULTI
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MS27472T24B4P | CONN RCPT 56POS WALL MT W/PINS |
| VE-B4H-MY-F1 | CONVERTER MOD DC/DC 52V 50W |
| VE-J0H-MZ-F2 | CONVERTER MOD DC/DC 52V 25W |
| VE-JVM-MZ-F3 | CONVERTER MOD DC/DC 10V 25W |
| VE-J10-MZ-F4 | CONVERTER MOD DC/DC 5V 25W |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
|---|---|
| SI5368C-C-GQR | 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� Precision Clk Xplier Jitter Attn 4In/5Out RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel |
| SI5368-EVB | 鍒堕€犲晢:Silicon Laboratories Inc 鍔熻兘鎻忚堪: |
| Si5369A-C-GQ | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘鍝� LW LOOP BW AR CLK MULT/JITTER 4IN 5OUT RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
| SI5369A-C-GQR | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘鍝� Lo Loop BW Clk Multi Jitter Attn 4In/5Out RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
| Si5369B-C-GQ | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘鍝� LW LOOP BW AR CLK MULT/JITTER 4IN 5OUT RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
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