- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373397 > SII141 (Electronic Theatre Controls, Inc.) SiI 141B PanelLink Digital Receiver PDF資料下載
參數(shù)資料
| 型號： | SII141 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiI 141B PanelLink Digital Receiver |
| 中文描述： | 精工141B章PanelLink數(shù)字接收機(jī) |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | SII141 |
Output Pin Description
Pin Name
Q35 – Q0
SiI 141B
Diagram
SiI 141B
SiI-DS-0037-C
Silicon Image, Inc.
7
Subject to Change without Notice
Pin #
See
Type
Out
Description
Output Data [35:0].
Output data is synchronized with output data clock (ODCK).
When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel data.
When PIXS is high Q17-Q0 output the even numbered pixels (pixel 0, 2, 4, ... , etc.) and Q35-Q18 output
the odd numbered pixels (pixel 1, 3, 5, ... , etc.).
Refer to the TFT Signal Mapping (Si
I
/AN-0008) and DSTN Signal Mapping (Si
I
/AN-0007) application notes
which tabulate the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Output Data Clock.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Output Data Enable.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This pin is
not
controlled by PDO.
General output control signal 3.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Pin
ODCK
36
Out
DE
41
Out
HSYNC
VSYNC
CTL1
CTL2
CTL3
12
14
8
9
10
Out
Out
Out
Out
Out
Configuration Pin Description
Pin Name
Pin #
OCK_INV
Type
In
Description
ODCK Polarity. A low level selects normal ODCK output, which enables data latching on the falling
edge. A high level (3.3V) selects inverted ODCK output, which enables data latching on the rising edge.
Both conditions are for color TFT panel support. For color 24-bit DSTN panel support, please refer to the
DSTN Signal Mapping (Si
I
/AN-0008-A) application note.
Pixel Select. A low level indicates that output data is one pixel (up to 24-bit) per clock and a high level
(3.3V) indicates that output data is two pixels (up to 36-bit) per clock.
Output Data Format. This pin controls clock and data output format. A low level indicates that ODCK
runs continuously for color TFT panel support and a high level (3.3V) indicates that ODCK is stopped
(LOW) for color 24-bit DSTN panel support when DE is low. Refer to the TFT Signal Mapping (Si
I
/AN-
0007-A) and DSTN Signal Mapping (Si
I
/AN-0008-A) application notes for a table on TFT or DSTN panel
support.
A low level enables the HSYNC de-jitter circuitry. A high level disables the de-jitter circuitry. If left
unconnected, the circuitry defaults to disabled.
Output Driver Strength. A low level indicates low drive. A high level indicates high drive.
80
PIXS
5
In
DF0
6
In
HSYNC_DEJTR
75
In
ST
79
In
Power Management Pin Description
Pin Name
Pin #
Type
SCDT
7
Out
Description
SyncDetect. A high level is output when DE is toggling. A low level is output when DE is inactive. See page
9.
Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down
mode. During power down mode all internal circuitry is powered down and digital I/O are set the same as
when PDO is asserted. (see PDO pin description).
Power Down Output (active low). A high level indicates normal operation. A low level puts the output drivers
only into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
There is an internal pull-up resistor on PDO that defaults the chip to normal operation if left unconnected.
SCDT and CTL1 are not tri-stated by this pin. See explanation of clock detect on page 8-9.
PD
2
In
PDO
3
In
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII141B | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 536-0101-9 00; No. of Positions: 2; Connector Type: Board mounting; Contact Gender: Male; Contact Spacing (mm): 1.25; Terminal Pitch (mm): 1.25; PCB Mount Type: Through-hole; Current Rating(Amps)(Max.): 1; Contact Mating Area Plating: Tin; Operating Temperature Range (degrees C): -35 to 85; General Description: Header; Straight; Single row |
| SII150A | PanelLink Digital Transmitter |
| SiI150ACT100 | PanelLink Digital Transmitter |
| SIL15C | 5Vin and 12Vin single output |
| SIL15C-05SADJV | 5Vin and 12Vin single output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII141B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SiI 141B PanelLink Digital Receiver |
| SII145S12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:絕緣柵雙極型晶體管（IGBT）Isolated Gate Bipolar Transistor (IGBTs)，SPT技術(shù)的IGBT模塊SPT IGBT Modules (Soft Punch Through Technology)。 |
| SII150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PanelLink Digital Transmitter |
| SII150ACT100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PanelLink Digital Transmitter |
| SII150N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。