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參數(shù)資料
| 型號： | SII141 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiI 141B PanelLink Digital Receiver |
| 中文描述： | 精工141B章PanelLink數(shù)字接收機(jī) |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | SII141 |
Differential Signal Data Pin Description
Pin Name
Pin #
Type
RX0+
70
Analog
RX0-
71
RX1+
67
RX1-
68
RX2+
64
RX2-
65
RXC+
74
Analog
RXC-
73
EXT_RES
76
Analog
SiI 141B
SiI-DS-0037-C
Silicon Image, Inc.
8
Subject to Change without Notice
Description
TMDS Low Voltage Differential Signal input data pairs.
TMDS Low Voltage Differential Signal input clock pair.
Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable.
In the common case of 50
transmission line, an external 530
resistor must be connected between AVCC
and this pin.
Reserved Pin Description
Pin Name
Pin #
RSVD
1
Power and Ground Pin Description
Pin Name
Pin #
VCC
39
50
61
GND
11
Ground Digital GND.
37
62
OVCC
15
28
48
OGND
4
Ground Output GND.
13
26
46
AVCC
63
69
AGND
66
Ground Analog GND.
72
PVCC
77
PGND
78
Ground PLL GND.
Application Information
The SiI141B is pin for pin compatible with the SiI141 but includes two new features, HSYNC de-jitter and power
down when the clock is inactive.
HSYNC de-jitter enables the 141B to operate properly even when the HSYNC signal contains jitter. Pin 75 is used
to enable or disable this capability (a reserved pin tied high on the SiI141). Tying this pin low enables the HSYNC
de-jitter circuitry while tying it high disables the circuitry. The HSYNC de-jitter circuitry operates normally with most
VESA standard timings. Some DOS mode resolutions do not have timings that are a multiple of eight (HSYNC
and VSYNC total times and front and back porch times are multiples of eight pixel times). If they are not a multiple
of eight, operation is not guaranteed and the HSYNC de-jitter circuitry should be turned off. When HSYNC de-
jitter is enabled, the circuitry will introduce anywhere from 0 to 7 CLK delays in the HSYNC signal relative to the
output data.
The SiI141B includes a new power saving feature, power down with clock detect circuit. The SiI141B will go into a
low power mode when there is no video clock coming from the transmitter. In this mode the entire chip is powered
down except the clock detect circuitry. During this mode digital I/O are set to a high impedance (tri-state) mode. A
weak internal pull-down device brings each output to ground. The device power down and wake-up times are
shown in Figures 6 and 7.
The SiI141B also includes a sync detect feature for pin compatibility with SiI141. In both the SiI141 and SiI141B,
SCDT goes low when DE is inactive.
Type
Out
Description
This signal must be left unconnected.
Type
Power
Description
Core VCC, must be set to 3.3V.
Output VCC, must be set to 3.3V.
Power
Analog VCC, must be set to 3.3V.
Power
PLL VCC, must be set to 3.3V.
Power
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII141B | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 536-0101-9 00; No. of Positions: 2; Connector Type: Board mounting; Contact Gender: Male; Contact Spacing (mm): 1.25; Terminal Pitch (mm): 1.25; PCB Mount Type: Through-hole; Current Rating(Amps)(Max.): 1; Contact Mating Area Plating: Tin; Operating Temperature Range (degrees C): -35 to 85; General Description: Header; Straight; Single row |
| SII150A | PanelLink Digital Transmitter |
| SiI150ACT100 | PanelLink Digital Transmitter |
| SIL15C | 5Vin and 12Vin single output |
| SIL15C-05SADJV | 5Vin and 12Vin single output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII141B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SiI 141B PanelLink Digital Receiver |
| SII145S12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:絕緣柵雙極型晶體管（IGBT）Isolated Gate Bipolar Transistor (IGBTs)，SPT技術(shù)的IGBT模塊SPT IGBT Modules (Soft Punch Through Technology)。 |
| SII150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PanelLink Digital Transmitter |
| SII150ACT100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PanelLink Digital Transmitter |
| SII150N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
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