參數(shù)資料
型號(hào)： SM59264
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 - Bit Micro-controller
中文描述： 8 -位微控制器
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 579K
代理商： SM59264
May 2002
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/32 Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc. SM59264
To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page
erase function, SM59264 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located
within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $X(Y+1)FF (Y: even number), or
page erase function will erase from $X(Y-1)00 to $XYFF (Y: odd number)
To perform the chip erase ISP function, SM59264 will erase all the flash program memory and data flash memory except
the ISP service program space if lock bit N been configured. Also, SM59264 will un-protect the flash memory automati-
cally. To perform chip protect ISP function, all the flash memory will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV ISPFD, #55H
MOV ISPFD, #AAH
MOV ISPFD, #55H
MOV $BF, #04H ; enable SM59264 ISP function
MOV $F4, #10H ; set flash address-high, 10H
MOV $F5, #05H ; set flash address-low, 05H
MOV $F6, #22H ; set flash data to be programmed, data = 22H
MOV $F7, #80H ; start to program #22H to the flash address $1005H
; after byte program finished, START bit of FCR will be reset to 0 automatically
; program counter then point to the next instruction
4. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is differ-
ent from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clear-
ing the WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is
independent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically
when SM59264 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
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