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參數(shù)資料
| 型號： | SM59264 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 - Bit Micro-controller |
| 中文描述： | 8 -位微控制器 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 579K |
| 代理商： | SM59264 |
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May 2002
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/32 Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc. SM59264
Watch Dog Timer Register - System Control Register (SCONF, $BF)
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
5. Reduce EMI Function
The SM59264 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module contains 1 kind of PWM sub module: SPWM (Specific PWM).
SPWM has four 8-bit channels.
6.1 SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(SPFS[1:0]+1).
The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(SPFS[1:0]+1)]/32.
6.2 SPWM Registers - P1CON, SPWMC, SPWMD[3:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
SPWME[3:0]: When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to
zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
bit-7
bit-0
Read :
Write :
Reset value :
WDR
Unused
Unused
Unused
DFEN
ISPE
OME
ALEI
0
*
*
*
0
0
0
0
bit-7
bit-0
Read:
Write:
Reset value:
Unused
Unused
SPWME3
SPWME2
SPWME1
SPWME0
Unused
Unused
*
*
0
0
0
0
*
*
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| SM59264_06 | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8-Bits Micro-controller with 128KB flash & 1KB RAM & TWSI & SPWM embedded |
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