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參數(shù)資料
| 型號(hào)： | SN54ABT834 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit To 9-Bit Parity Bus Transceivers(8-9奇偶總線收發(fā)器) |
| 中文描述： | 8位到第9位奇偶總線收發(fā)器（8-9奇偶總線收發(fā)器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 142K |
| 代理商： | SN54ABT834 |
SN54ABT834, SN74ABT834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS168 – FEBRUARY 1991–REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
7 V
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7 V
Open
tPLH
tPHL
Output
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
3.5 V
3 V
0 V
1.5 V
1.5 V
VOH
VOL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈
0 V
3 V
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
ERR
tPHL (see Note E)
tPLH (see Note F)
S1
Open
7 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Zo = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. tPHL is measured at 1.5 V.
F. tPLH is measured at VOL + 0.3 V.
Figure 1. Load Circuit and Voltage Waveforms
P
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