參數(shù)資料
型號(hào): SN54LS165
廠商: Motorola, Inc.
英文描述: 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER
中文描述: 8位并行到串行移位寄存器
文件頁(yè)數(shù): 4/6頁(yè)
文件大小: 207K
代理商: SN54LS165
5-293
FAST AND LS TTL DATA
SN54/74LS165
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
tW
ts
ts
ts
th
trec
CP Clock Pulse Width
25
ns
VCC = 5.0 V
PL Pulse Width
15
ns
Parallel Data Setup Time
10
ns
Serial Data Setup Time
CP1 to CP2 Setup Time1
Hold Time
20
ns
30
ns
0
ns
Recovery Time, PL to CP
45
ns
1The role of CP1, and CP2 in an application may be interchanged.
DEFINITION OF TERMS:
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative hold time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the PL pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer loaded Data to the Q outputs.
AC WAVEFORMS
Figure 1
Figure 3
Figure 2
Figure 4
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