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參數(shù)資料
| 型號： | SN74ABT18504PMRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| 封裝： | GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 505K |
| 代理商： | SN74ABT18504PMRG4 |
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SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
19
boundary-control register opcode description (continued)
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs andapplied to the inputs of the normal on-chip logic. At the same
time, a 20-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 8 and 9 illustrate the 20-bit linear-feedback shift-register algorithms through
which the signature and patterns are generated. An initial seed value should be scanned into the boundary-scan
register prior to performing this operation. A seed value of all zeroes will not produce additional patterns.
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
B10-O
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
A8-I
A10-I
A17-I
A16-I
A15-I
A14-I
A13-I
A12-I
A11-I
A18-I
A20-I
B18-O
B17-O
B16-O
B15-O
B14-O
B13-O
B12-O
B11-O
B20-O
B9-O
A9-I
A19-I
B19-O
=
MASKX
=
Figure 8. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)
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| SN74ABT18640 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS |
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