參數(shù)資料
型號: SN74ABTH1826520A
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測裝置帶18位總線收發(fā)器和寄存器)
中文描述: 掃描測試設備與18位通用總線收發(fā)器和寄存器(掃描檢測裝置帶18位總線收發(fā)器和寄存器)
文件頁數(shù): 15/36頁
文件大?。?/td> 848K
代理商: SN74ABTH1826520A
SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D – AUGUST 1993 – REVISED JULY 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O
BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on
each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at
the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a RUNT operation to specify which test operation is to be executed.
相關(guān)PDF資料
PDF描述
SN54ABTH18652A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置,帶18位總線收發(fā)器和寄存器)
SN54ABTH245FK OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABTH245DB OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABTH245DGV OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABTH245PW OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
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