參數(shù)資料
型號(hào): SN74ABTH1826520A
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測(cè)裝置帶18位總線收發(fā)器和寄存器)
中文描述: 掃描測(cè)試設(shè)備與18位通用總線收發(fā)器和寄存器(掃描檢測(cè)裝置帶18位總線收發(fā)器和寄存器)
文件頁(yè)數(shù): 7/36頁(yè)
文件大?。?/td> 848K
代理商: SN74ABTH1826520A
SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D – AUGUST 1993 – REVISED JULY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals are all passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
Figure 2. TAP-Controller State Diagram
相關(guān)PDF資料
PDF描述
SN54ABTH18652A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測(cè)裝置,帶18位總線收發(fā)器和寄存器)
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