參數(shù)資料
型號： SN74ALVC16841
廠商： Texas Instruments, Inc.
英文描述： 20-Bit Bus-Interface D-Type Latches(20位總線接口D鎖存器（三態(tài)輸出）)
中文描述： 20位總線接口D類鎖存器（20位總線接口?鎖存器（三態(tài)輸出））
文件頁數(shù)： 1/5頁
文件大?。?/td> 93K
代理商： SN74ALVC16841
SN74ALVC16841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS274 – JANUARY 1993 – REVISED MARCH 1994
Copyright
1994, Texas Instruments Incorporated
9–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50
or Greater
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 20-bit bus-interface D-type latch is designed
for 2.7-V to 3.6-V V
CC
operation.
The SN74ALVC16841 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The SN74ALVC16841 can be used as two 10-bit
latches or one 20-bit latch. The twenty latches are
transparent D-type latches. The device has
noninverting data (D) inputs and provides true
data at its outputs. While the latch-enable (1LE or
2LE) input is high, the Q outputs of the
corresponding 10-bit latch follow the D inputs.
When LE is taken low, the Q outputs are latched
at the levels that were set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The output-enable (OE) input does not affect the internal operation of the latches. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The SN74ALVC16841 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC16841 is characterized for operation from –40
°
C to 85
°
C.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
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1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2LE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
P
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