CGM Method of Operation
MOTOROLA
On-Chip Clock Synthesis (OCCS)
6-9
Preliminary
6
6.8.1.2.1 Lock Time Determination
Typical control systems refer to the lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL the step input occurs when the PLL is
turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of
the step input or when the output settles to the desired value plus or minus a percent of the
frequency change. Therefore, the reaction time is constant in this definition regardless of
the size of the step input.
When the PLL is coming from a powered down state (PDN is high) to a powered up
condition (PDN is low) the maximum lock time is 10msec.
Other systems refer to lock time as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the lock
time varies according to the original error in the output. Minor errors may be shorter or
longer in many cases.
6.8.1.2.2 Parametric Influences on Reaction Time
Lock time is designed to be as short as possible while still providing the highest possible
stability. The reaction time is not constant, however. Many factors directly and indirectly
affect the lock time.
The most critical parameter affecting the reaction time of the PLL, is the Reference
Frequency (FREF). This frequency is the input to the phase detector and controls how
often the PLL makes corrections. For stability, the corrections must be small compared to
the desired frequency, so several corrections are required to reduce the frequency error.
Therefore, the slower the reference, the longer it takes to make these corrections. This
parameter controlled by the user via the choice of OSC Clock Frequency (FOSC).
Temperature and processing also can affect acquisition time because the electrical
characteristics of the PLL change. The part operates as specified as long as these
influences stay within the specified limits.
6.8.1.3 PLL Frequency Lock Detector
This digital block monitors the VCO output clock and sets the LCK1 and LCK0 bits in the
CGM Control register based on the frequency accuracy. The lock detector is enabled with
the LCKON bit of the CGMCR as well as the PDN bit. Once enabled, the detector starts
two counters whose outputs are periodically compared. The input clocks to these counters
are the VCO output clock divided by the divide-by factor, feedback, and the crystal
reference clock, OSC clock. The period of the pulses being compared cover one whole
period of each clock because the feedback clock doesn’t guarantee a 50 percent duty
cycle.