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參數(shù)資料
| 型號： | SPB-3018 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 400 - 2500 MHz 1W Medium Power Active Bias InGaP/GaAs HBT Amplifier |
| 中文描述： | 400 - 2500兆赫1W的中等功率有源偏置的InGaP / GaAs HBT的放大器 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 205K |
| 代理商： | SPB-3018 |
Broomfield, CO 80021
8
EDS-103980 Rev C
SPB-3018 400-2500 MHz Cascadable MMIC Amplifier
Preliminary
303 S. Technology Ct.
Phone: (800) SMI-MMIC http://www.sirenza.com
ESD Class 1B, 500V HBM
Appropriate precautions in handling, packaging
and testing devices must be observed.
Absolute Maximum Ratings
MSL
(Moisture Sensitivity Level)
Rating: Level 1
Simplified Device Schematic
Parameter
Absolute Limit
Max Device Current (I
DQ
)
Max Device Voltage (V
D
)
Max. RF Input Power
Max. Operating Dissipated
Power (quiescent)
Max. Junction Temp. (T
J
)
Operating Temp. Range (T
L
)
Max. Storage Temp.
400 mA
6 V
+26 dBm
2.0 W
+150°C
-40°C to +85°C
+150°C
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation, the device
voltage and current must not exceed the maximum operating
values specified in the table on page one.
Bias Conditions should also satisfy the following expression:
I
D
V
D
< (T
J
- T
L
) / R
TH
, j-l T
L
=T
LEAD
Pin #
Function
Description
1
Vbias
Vbias is the bias control pin for the active bias network. Recommended configuration is shown
in the Application Schematic.
V
PC
is the bias control pin for the active bias network.
RF input pin. This pin requires the use of an external DC blocking capacitor as shown in the
Application Schematic.
2
V
PC
3
RF IN
4
N/C
5,6,7,8
RF OUT/
BIAS
RF output and bias pins. Bias should be supplied to this pin through an external RF choke.
Because DC biasing is present on this pin, a DC blocking capacitor should be used in most
applications (see application schematic). The supply side of the bias network should be well
bypassed. An output matching network is necessary for optimum performance.
EPAD
GND
Exposed area on the bottom side of the package needs to be soldered to the ground plane of
the board for thermal and RF performance. Several vias should be located under the EPAD as
shown in the recommended land pattern (page 9).
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