參數(shù)資料
型號(hào)： SPC5200CVR400R2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/72頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝： 500
系列： MPC52xx
處理器類型： 32-位 MPC52xx PowerPC
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
19
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
1.3.6.3
Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value
is calculated automatically by hardware.
Table 20. DDR SDRAM Memory Read Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk
MEM_CLK period
7.5
—
ns
A5.15
tvalid
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
—tmem_clk ×0.5 +0.4
ns
A5.16
thold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
tmem_clk × 0.5
—
ns
A5.17
datasetup
Setup time relative to MDQS
—
0.4
ns
A5.18
datahold
Hold time relative to MDQS
2.6
—
ns
A5.19
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
WRITE
NOP
thold
Row
Column
MBA (Bank Selects)
datahold
datavalid
tvalid
thold
tvalid
thold
tvalid
DQM (Data Mask)
DMvalid
DMhold
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