參數(shù)資料
型號： SPC5200CVR400R2
廠商： Freescale Semiconductor
文件頁數(shù)： 33/72頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝： 500
系列： MPC52xx
處理器類型： 32-位 MPC52xx PowerPC
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
39
Figure 28. Ethernet Timing Diagram—MII Tx Signal
Figure 29. Ethernet Timing Diagram—MII Async
Table 32. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t5
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
invalid
5—
ns
A9.5
t6
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
A9.6
t7
TX_CLK pulse width high
35%
65%
TX_CLK Period(1)
1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
A9.7
t8
TX_CLK pulse width low
35%
65%
TX_CLK Period(1)
A9.8
Table 33. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t9
CRS, COL minimum pulse width
1.5
—
TX_CLK Period
A9.9
t8
t7
t5
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
t6
t9
CRS, COL
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