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參數(shù)資料
| 型號(hào)： | ST16C2552IJ44-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 23/34頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 3.3 V ~ 5 V |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 1016-1258-5 |
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ST16C2552
3
REV. 4.2.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
20
I
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
18
I
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between
the user CPU and the 2552.
CHSEL
16
I
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
34
O
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures
INTB
17
O
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures
TXRDYA#
1
O
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A.
If it is not used, leave it
unconnected.
TXRDYB#
32
O
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2552IJ44TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2552IQ48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| ST16C32245 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245LBR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245TBR | 功能描述:總線收發(fā)器 14 BIT DUAL BUS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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