- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3763 > ST16C2552IJ44-F (Exar Corporation)IC UART FIFO 16B DUAL 44PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | ST16C2552IJ44-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 33/34頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 3.3 V ~ 5 V |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 1016-1258-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁
ST16C2552
8
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2.2
2.4
Channel A and B Internal Registers
Each UART channel in the 2552 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2552 offers the Alternate Function Register which
allows simultaneous writes to both channels. All the register functions are discussed in full detail later in
2.5
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be exercised, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2552 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. The following table show their behavior. Also see
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C2552CJ44-F | IC UART FIFO 16B DUAL 44PLCC |
| XR88C681CJ-F | IC UART CMOS DUAL 44PLCC |
| XR16M2550IM48-F | IC UART FIFO 16B 1.8V DL 48TQFP |
| ST16C552CJ68-F | IC UART FIFO PAR 16B DUAL 68PLCC |
| XR16L2752IJ-F | IC UART FIFO 64B DUAL 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2552IJ44TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2552IQ48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| ST16C32245 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245LBR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245TBR | 功能描述:總線收發(fā)器 14 BIT DUAL BUS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。