- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1970 > ST16C580IQ48-F (Exar Corporation)IC UART FIFO 16B 48TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ST16C580IQ48-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 13/39頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)
ST16C580
20
Rev. 1.22
Table 6, INTERRUPT SOURCE TABLE
Priority
[ ISR BITS ]
Level
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
000110
LSR (Receiver Line Status Register)
2
000100
RXRDY (Received Data Ready)
2
001100
RXRDY (Receive Data time out)
3
000010
TXRDY ( Transmitter Holding Register Empty)
4
000000
MSR (Modem Status Register)
5
010000
RXRDY (Received Xoff signal)/ Special character
6
100000
CTS, RTS change of state
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) are received.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFO’s
are enabled
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condition)
These two bits specify the word length to be transmitted
or received.
BIT-1
BIT-0
Word length
00
5
01
6
10
7
11
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C650AIJ44-F | IC UART FIFO 32B 44PLCC |
| ST16C654DIQ64-F | IC UART FIFO 64B QUAD 64LQFP |
| ST78C34CJ44-F | IC UART FIFO 83B 44PLCC |
| ST78C36ACJ44-F | IC UART FIFO 16B 44PLCC |
| SW06GSZ-REEL | IC SWITCH QUAD SPST 16SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C650 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A_0508 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650ACJ44 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。