參數(shù)資料
型號(hào)： ST16C580IQ48-F
廠商： Exar Corporation
文件頁數(shù)： 16/39頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
ST16C580
23
Rev. 1.22
device that the 580 is connected to. Four bits of this
register are used to indicate the changed information.
These bits are set to a logic 1 whenever a control input
from the modem changes state. These bits are set to a
logic 0 whenever the CPU reads this register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the 580 has changed state
since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-1:
Logic 0 = No -DSR Change (normal default condition)
Logic 1 = The -DSR input to the 580 has changed state
since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-2:
Logic 0 = No -RI Change (normal default condition)
Logic 1 = The -RI input to the 580 has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No -CD Change (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
-CTS functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding
register flow control is enabled/disabled by MSR bit-4.
Flow control (when enabled) allows the starting and
stopping the transmissions based on the external
modem -CTS signal. A logic 1 at the -CTS pin will stop
580 transmissions as soon as current character has
finished transmission.
Normally MSR bit-4 bit is the compliment of the -CTS
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to the OP1 bit in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to the OP2 bit in the MCR register.
Scratchpad Register (SPR)
The ST16C580 provides a temporary data register to
store 8 bits of user information.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this
register.
Bits-0 through 4 provide single or dual character
software flow control selection. When the Xon1 and
Xon2 and/or Xoff1 and Xoff2 modes are selected, the
double 8-bit words are concatenated into two sequen-
tial characters.
EFR BIT 0-3: (logic 0 or cleared is the default condi-
tion)
Combinations of software flow control can be selected
by programming these bits.
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