
50/72
ST62T45B/E45B
LCD CONTROLLER-DRIVER (Continued)
Figure 29. Typical Network to connect to VLCD
pins if VLCD
≤ 4.5V
Typical External resistances values are in the
range of 100 k
to 150 k. External capacitances
in the range of 10 to 47 nF can be added to VLCD
2/3 and VLCD 1/3 pins and to VLCD if the VLCD con-
nection is highly impedant.
4.5.3 LCD RAM
LCD RAM is organised as a LCD panel with a ma-
trix architecture. Each bit of its content is logically
mapped to a physical element of the display panel
addressed by a couple (Segment;Common). If a
bit is set, the relevant element of the LCD matrix is
turned-on. On the contrary, an element remains
turned-off as long the associated bit within the
LCD RAM is kept cleared.
After a reset, the LCD RAM is not initialised and
contain arbitrary information.
If the choosen multiplexing ratio does not use
some common plates, corresponding RAM ad-
dresses are free for general purpose data storage.
Figure 30. Addressing Map of the LCD RAM
VLCD
R
VLCD1/3
VSS
VLCD2/3
C
R: 100k
R
C
C: 47nF
VR01840
RAM Address
MSB
LSB
E0
E1
E2
E3
E4
E5
S8
S16
S24
S32
S40
S48
S7
S15
S23
S31
S39
S47
S6
S14
S22
S30
S38
S46
S5
S13
S21
S29
S37
S45
S4
S12
S20
S28
S36
S44
NA
S11
S19
S27
S35
S43
NA
S10
S18
S26
S34
S42
NA
S9
S17
S25
S33
S41
COM1
E6
E7
E8
E9
EA
EB
S8
S16
S24
S32
S40
S48
S7
S15
S23
S31
S39
S47
S6
S14
S22
S30
S38
S46
S5
S13
S21
S29
S37
S45
S4
S12
S20
S28
S36
S44
NA
S11
S19
S27
S35
S43
NA
S10
S18
S26
S34
S42
NA
S9
S17
S25
S33
S41
COM2
EC
ED
EE
EF
F0
F1
S8
S16
S24
S32
S40
S48
S7
S15
S23
S31
S39
S47
S6
S14
S22
S30
S38
S46
S5
S13
S21
S29
S37
S45
S4
S12
S20
S28
S36
S44
NA
S11
S19
S27
S35
S43
NA
S10
S18
S26
S34
S42
NA
S9
S17
S25
S33
S41
COM3
F2
F3
F4
F5
F6
F7
S8
S16
S24
S32
S40
S48
S7
S15
S23
S31
S39
S47
S6
S14
S22
S30
S38
S46
S5
S13
S21
S29
S37
S45
S4
S12
S20
S28
S36
S44
NA
S11
S19
S27
S35
S43
NA
S10
S18
S26
S34
S42
NA
S9
S17
S25
S33
S41
COM4
49