參數(shù)資料
型號： ST62T40B
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù)： 44/72頁
文件大?。?/td> 445K
代理商： ST62T40B
44/72
44
ST62T40B/E40B
4.3 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converterwith analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
The ADC uses two registersin the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write onlybit, anyattempt to read it will show a log-
ical “0”.
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done bysetting the PDS bit in theADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered anden-
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, thecontrol register is reset to 40h and the
ADC interrupt is masked (EAI=0).
Figure 24. ADC Block Diagram
4.3.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±
1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When selected asan analog channel, the input pin
is internally connected to a capacitor C
ad
of typi-
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5
μ
s) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5
μ
s = 9 x C
ad
x ASI
(capacitor charged to over 99.9%), i.e. 30 k
in-
cluding a 50% guardband. ASI can behigher if C
ad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
CONTROL REGISTER
CONVERTER
VA00418
RESULT REGISTER
RESET
AV
AV
DD
INTERRUPT
CLOCK
Ain
8
CORE
CONTROL SIGNALS
SS
8
CORE
相關(guān)PDF資料
PDF描述
ST62T10 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER
ST62T28C 8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
ST6228CN1 ER 3C 3#16S SKT RECP WALL
ST6228CN3 CB 5C 5#16S PIN RECP WALL
ST6228CN6 ER 5C 5#16S PIN RECP WALL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST62T40BQ6 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST62T42BQ6 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST62T45BQ6 功能描述:8位微控制器 -MCU OTP EPROM 8K RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST62T45Q6 制造商:STMicroelectronics 功能描述:8BIT MCU - Bulk
ST62T46BB6 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*