參數(shù)資料
型號(hào): ST62T40B
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù): 52/72頁(yè)
文件大?。?/td> 445K
代理商: ST62T40B
52/72
52
ST62T40B/E40B
4.6 POWERSUPPLY SUPERVISOR DEVICE (PSS)
The Power Supply Supervisordevice, described in
the Figure 32, permits supervising the crossing of
the PSS pin voltage (VPSS) through a program-
mable voltage (mxV
DD
/n), where n and m can be
chosen by software. This device includes:
– Aninternal comparator whichisconnected to the
internal INT line to make an interrupt request to
the Core.
– 2resistive voltagedividers that are,respectively,
supplied by the PSS pin and the V
DD
pin. These
two voltage dividers are both connected to the
two inputs of the internal comparator. They con-
sist of 13 identical resistors. It is possible to se-
lect by software 5 voltage rates on the PSS
divider (nxVPSS/13) and 4 voltage rates on the
V
DD
divider(mxV
DD
/13). The nand m values can
be chosen by software. These two voltage divid-
ers are disconnected in STOP mode, and when
the PSS device is OFF.
– An internal device that allows the detection with
an hysteresis of V
DD
/13.
The PSS device is supplied by an internal connec-
tion to V
DD
supply. The following paragraphs de-
scribe the operating mode of the PSS device and
the PSS registerthat permits control over the PSS
device. ThePSS device is switched off as soon as
the Core executes the STOP instruction, but con-
tinues to work in the WAIT mode.
Figure
Description
31. PSS
Device Operating Modes
Figure 32. PSS Device Block Diagram
VPSS
t
(m+1)x/V
DD
/13
mx/V
DD
/13
PIF
1
0
t
nxVPSS/13
VR02044A
PSS
V
DD
PSS ON
INTERRUPT LINE
PIF
2k
(UP to 13 STEPS)
2k
(UP to 13 STEPS)
SEQUENCER
& LOGIC
SYNCHRO
+
-
VA0060
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