參數(shù)資料
型號: ST62T40B
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁數(shù): 7/72頁
文件大?。?/td> 445K
代理商: ST62T40B
7/72
ST62T40B/E40B
1.2 PIN DESCRIPTIONS
V
and V
. Power is supplied to the MCU via
these two pins. V
is the power connection and
V
SS
is the ground connection.
OSCin and OSCout.
These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET
. The active-low RESET pin is used to re-
start the microcontroller.
TEST/V
.
The TEST must be held at V
for nor-
mal operation (an internal pull-down resistor se-
lects normal operating mode if TEST pin is not
connected). If TEST pin is connected to a +12.5V
level during the reset phase, the EPROM/OTP
programming Mode is entered.
NMI.
The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive with Schmitt trigger charac-
teristics. The user can select as option the availa-
bility of an on-chip pull-up at this pin.
PA0-PA7.
These 8 lines are organised as one I/O
port (A). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull output, or
as analog inputs for the A/D converter.
PB0...PB7.
These8 lines areorganised as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs,
analog inputsfor theA/D converter. PB0..PB3 can
be used as analog inputs for the A/D converter ,
while PB7/Sout, PB6/Sin and PB5/Sclcan be used
respectively as data out, data in and Clock pins for
the on-chip SPI. In addition, PB4..PB7 can sink
20mA for direct LED or TRIAC drive.
PC0-PC7
. These 8 lines are organised as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, input with interrupt generation and
pull-up resistor, open-drain or push-pull output, or
as LCD segment output S33..S40.
TIMER
. This is the TIMER 1 I/O pin. In input mode,
it is connected to the prescaler and acts as ex-
ternal timer clock or as control gate for the internal
timer clock.In output mode, the TIMER pin outputs
the data bit when a time-out occurs.The user can
select as option the availability of an on-chip pull-
up at this pin.
COM1-COM4
. These four pins are the LCD pe-
ripheral common outputs. They are the outputs of
the on-chip backplane voltage generator which is
used for multiplexing the 45 LCD lines allowing up
to 180 segments to be driven.
S4-S48
. These pins are the 45 LCD peripheral
segment outputs. S33..S40 are alternate functions
of the Port C I/O pins. (Combiports feature)
VLCD
. Display voltage supply. It determines the
high voltage level on COM1-COM4 and S4-S48
pins.
VLCD1/3, VLCD2/3
. Display supply voltage inputs
for determining the display voltage levels on
COM1-COM4 and S4-S48 pins during multiplex
operation.
PSS
. Thisis the Power Supply Supervisor sensing
pin. When the voltage applied to this pin is falling
below a software programmed value the highest
priority (NMI) interrupt can be generated. This pin
has to be connected to the voltage to be super-
vised.
OSC32in
and
OSC32out
. These pins are inter-
nally connected with the on-chip 32kHz oscillator
circuit. A 32.768kHz quartz crystal can be con-
nected between these two pins if it is necessary to
provide theLCD stand-by clock and real time inter-
rupt. OSC32in is the input pin, OSC32out is the
output pin.
WDON
. This pin is an alternate and external
source of controlling the watchdog activation, in-
dependantly of the options set into the MCU by the
user. A low level selects the hardware activated
watchdog, while a high level selects the software
activated watchdog for low consumption modes.
This pin overcomes the option byte content. How-
ever ifWDON pinstate is different from optionbyte
content, extra consumption must be expected.
7
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