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參數(shù)資料
| 型號： | ST6391 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| 中文描述： | 8位微控制器HCMOS電視頻率合成帶OSD |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 560K |
| 代理商： | ST6391 |
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During transmission or reception of data, all ac-
cess to serial data register is therefore disabled.
The reception or transmission of data is started by
setting the BUSY bit to “1”; this will be automat-
ically reset at the end of the operation.After reset,
the busy bitis cleared to “0”, and the hardwareSPI
disabled by clearing bit 0 and bit 1 of SPI control
register 1 to “0”. The outputs from the hardware
SPI are“ANDed” to the standard I/Osoftware con-
trolled outputs.If the hardware SPI is in operation
the PortC pinsrelated to the SPIshould beconfig-
ured as outputs using the Data Direction Register
and shouldbe sethigh.WhentheSPIisconfigured
as the S-BUS, the three pins PC0, PC1 and PC3
become the pins SCL, SDAand SENrespectively.
When configuredas the I
2
CBUS thepins PC0 and
PC1 areconfiguredasthe pinsSCLand SDA;PC3
is notdriven andcan beused asageneralpurpose
I/O pin. In the case of the STD SPI the pins PC0
and PC1 become the signals CLOCK and DATA,
PC3 isnot driven and can be usedas general pur-
pose I/Opin. The VERIFYbit isavailablewhen the
SPI is configured as either S-BUS or I
2
CBUS. At
the startof a byte transmission,the verify bitis set
to one.Ifat any time during thetransmissionof the
following eight bits, the data on the SDA line does
not matchthe data forcedby the SPI(while SCL is
high), then the VERIFY bit is reset. The verify is
available only during transmission for the S-BUS
and I
2
CBUS; for other protocol it is not defined.
The SDAandSCL signalentering theSPI arebuff-
ered in order to removeany minor glitches. When
STD bit is set to one (S-BUS or I
2
CBUS selected),
and TRXbit is reset (receivingdata),and STOPbit
is set(last byte of currentcommunication), the SPI
interface does not generate the Acknowledge, ac-
cording to S-BUS/I
2
CBUS specifications. PCO-
SCL, PC1-SDA and PC3-SEN lines are standard
driveI/O port pinswith open-drainoutputconfigura-
tion (maximum voltage that can be appliedto these
pinsis V
DD
+ 0.3V).
S-BUS/I
2
CBUS ProtocolInformation
The S-BUS is a three-wire bidirectional data-bus
with functional features similar to the I
2
CBUS. In
fact the S-BUS includes decoding of Start/Stop
conditions and the arbitration procedure in case of
multimaster system configuration(the ST639x SPI
allows a single-master only operation). The SDA
line, in the I
2
CBUS represents the AND combina-
tion of SDAandSEN linesin theS-BUS.IftheSDA
and theSEN linesare short-circuitconnected,they
appear as the SDA line of the I
2
CBUS. The
Start/Stop conditions are detected (by the external
peripherals suited to work with S-BUS/I
2
CBUS) in
thefollowingway:
-
OnS-BUSbya transition of the SENline (1to0
Start,0 to 1 Stop)while the SCL line is at high
level.
-
On I
2
CBUS by a transitionof the SDA line (10
Start, 01Stop) while the SCL line is at high
level.
Start and Stop condition are always generated by
the master (ST639x SPI can only work as single
master).Thebusisbusyafterthestartconditionand
can be considered again free only when a certain
time delay is left after the stop condition. In the S-
BUS configuration the SDA line is only allowed to
changeduringthetimeSCL lineislow.Afterthestart
informationtheSENlinereturnstohighlevelandre-
mainsunchangedfor all the datatransmission time.
Whenthe transmission is completedthe SDAlineis
setto highleveland,at thesame time, theSENline
returnsto the low level inorderto supplythe stopin-
formationwith alow tohightransition,while the SCL
lineisathighlevel.OntheS-BUS,asontheI
2
CBUS,
each eight bit information (byte) is followed by one
acknowledged bit which is a high level put on the
SDA line by the transmitter. A peripheral that ac-
knowledgeshastopulldowntheSDAlineduringthe
acknowledge clock pulse. An addressed receiver
has to generatean acknowledgeafterthereception
of eachbyte;otherwise the SDAline remainsatthe
high level during the ninth clock pulse time.In this
case the master transmittercan generatethe Stop
condition, via the SEN (or SDAin I
2
CBUS) line, in
order to abortthe transfer.
SERIAL PERIPHERAL INTERFACE
(Continued)
ST6391,92,93,95,97,99
34/64
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6391B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6392 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6392B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
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