參數(shù)資料
型號(hào)： ST6391B1
廠商： 意法半導(dǎo)體
英文描述： MOSFET; Transistor Polarity:Dual N Channel; Continuous Drain Current, Id:2.6A; On-Resistance, Rds(on):0.18ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
中文描述： 8位微控制器HCMOS電視頻率合成帶OSD
文件頁數(shù)： 56/68頁
文件大小： 560K
代理商： ST6391B1
SOFTWARE DESCRIPTION
The ST63xx software has been designed to fully
use thehardwareinthemostefficientwaypossible
while keepingbyteusage toa minimum;in shortto
provide byte efficientprogramming capability.The
ST63xx Core has the ability to set or clear any
register or RAM locationbit ofthe Data space with
a single instruction.Furthermore, the programmay
branch to a selected address depending on the
status of any bit of the Data space. The carry bitis
stored with the value of the bit when the SET or
RES instructionis processed.
Addressing Modes
The ST63xx Core has nine addressing modes
which are described in the following paragraphs.
The ST63xx Core uses three different address
spaces : Program space, Data space, and Stack
space. Program space contains the instructions
which are to be executed,plus the data for imme-
diate mode instructions. Data space contains the
Accumulator,the X,Y,VandWregisters,peripheral
and Input/Outputregisters, the RAM locations and
Data ROM locations (for storage of tables and
constants). Stack space contains six 12-bit RAM
cells usedtostackthereturnaddressesforsubrou-
tines and interrupts.
Immediate.
In the immediate addressing mode,
the operand of the instruction follows the opcode
location. Asthe operand is a ROM byte,theimme-
diate addressingmode isusedtoaccessconstants
which do not change during program execution
(e.g., a constant used to initialize a loop counter).
Direct.
In the direct addressingmode, the address
of the byte that is processed by the instruction is
storedinthelocationthatfollowstheopcode.Direct
addressing allows the user to directly address the
256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct.
The Core can addressthe four RAM
registers X,Y,V,W(locations 80H, 81H, 82H, 83H)
in the short-direct addressing mode. In this case,
the instructionis only one byteand the selectionof
the location to be processed is contained in the
opcode. Short direct addressing is a subset of the
direct addressing mode. (Note that 80H and 81H
are alsoindirect registers).
Extended.
In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenatingthe four lesssignificant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) that use the
extended addressing mode are able to branch to
any addressof the 4K bytes Programspace.
An extended addressing mode instruction is two-
byte long.
ProgramCounter Relative.
The relative address-
ing modeis onlyusedinconditionalbranchinstruc-
tions.The instruction isused to performa testand,
if the condition is true, a branch with a span of -15
to +16locationsaround the addressof the relative
instruction. If the condition is not true, the instruc-
tion thatfollows the relativeinstructionis executed.
The relative addressing mode instruction is one-
byte long. The opcode is obtained in adding the
threemostsignificantbitsthatcharacterizethekind
of the test, one bit that determines whether the
branchisaforward(when itis0)orbackward(when
it is1) branch and the four less significantbits that
give thespan of thebranch (0h to Fh) that mustbe
added or subtracted to the address of the relative
instruction to obtain the address of the branch.
Bit Direct.
In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the bytefollowingthe opcodepoints totheaddress
of the bytein whichthe specifiedbit must be setor
cleared. Thus, any bit in the 256 locations of Data
space memory can be setor cleared.
Bit Test & Branch.
The bit test and branch ad-
dressing mode is a combinationof direct address-
ing andrelative addressing.The bittestand branch
instruction is three-byte long. The bit identification
and the testedconditionareincludedintheopcode
byte. The address of the byte to be tested follows
immediatelytheopcodeinthe Programspace.The
third byte is the jump displacement, which is in the
range of -126 to +129. This displacement can be
determined usingalabel,which isconvertedbythe
assembler.
Indirect.
In the indirect addressingmode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the
indirect registers, X or Y (80H,81H). The indirect
register is selected by the bit 4 of the opcode. A
register indirectinstruction is one byte long.
Inherent.
In the inherent addressing mode, all the
information necessaryto execute the instruction is
contained in the opcode. These instructions are
one byte long.
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ST6399 MOSFET; Transistor Polarity:P Channel; Drain Source Voltage, Vds:-30V; Continuous Drain Current, Id:-4.1A; On-Resistance, Rds(on):0.08ohm; Rds(on) Test Voltage, Vgs:-10V; Package/Case:8-1206; Leaded Process Compatible:No
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