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參數(shù)資料
| 型號： | ST6395 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| 中文描述： | 8位微控制器HCMOS電視頻率合成帶OSD |
| 文件頁數(shù)： | 24/68頁 |
| 文件大小： | 560K |
| 代理商： | ST6395 |
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INTERRUPT
(Continued)
TIMER 2 Interrupt (#1).
The TIMER 2 Interrupt is
connectedto theinterrupt #1(0FF6h).TheTIMER 2
interruptgeneratesalow level(whichislatchedinthe
timer). Onlythelowlevel selectionfor#1canbeused.
Bit6oftheinterruptoptionregisterC8hhastobeset.
VSYNC Interrupt (#2).
The VSYNC Interrupt is
connected to the interrupt #2. When disabled the
VSYNCINTsignal is low.The VSYNCINT signalis
inverted with respect to the signal applied to the
VSYNC pin. Bit 5 of the interrupt option register
C8h isused toselect thenegative edge (ES2=0)or
the positive edge (ES2=1); the edge will depend
on the application. Note that once an edge has
been latched, then the only way to remove the
latched signal is to service theinterrupt.Care must
be taken not to generate spurious interrupts. This
interrupt may be used for synchronize to the
VSYNCsignal in orderto change charactersin the
OSD only when the screen is on verticalblanking
(if desired). This methodmay also be used to blink
characters.
TIMER 1 Interrupt (#3).
The TIMER 1 Interruptis
connected to the fourth interrupt#3 (0FF2h) which
detectsa low level(latched in the timer).
PWR Interrupt (#4).
The PWR Interrupt is con-
nected to the fifth interrupt #4 (0FF0h). If the
PWRINT is disabled at the PWR circuitry, then it
will be high. The #4 interrupt input detects a low
level. A simple latch is provided from the PC4
(PWRIN)pin in orderto generatethe PWRINT sig-
nal. This latch can be triggered by either the posi-
tive or negative edge of the PWRIN signal.
PWRINT is inverted with respect to the latch. The
latch can be reset bysoftware.
Notes
Global disable does not reset edge sensi-
tive interruptflags. Theseedge sensitive interrupts
becomependingagainwhenglobaldisablingis re-
leased. Moreover, edge sensitive interrupts are
stored in therelated flags also when interrupts are
globallydisabled,unlesseachedge sensitiveinter-
rupt is also individually disabled before the inter-
rupting event happens. Global disable is done by
clearing the GEN bit of Interrupt option register,
while any individual disable is done in the control
register of the peripheral. The on-chip Timer pe-
ripheralshavean interruptrequestflagbit(TMZ),this
bitis settoonewhenthedevicewantstogeneratean
interruptrequestandamaskbit(ETI)thatmustbeset
toonetoallowthetransferoftheflagbittotheCore.
ST6391,92,93,95,97,99
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST6395B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6397 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6397B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6399 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6399B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
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