參數(shù)資料
型號(hào): ST72621J2B1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP20
封裝: 0.300 INCH, PLASTIC, DIP-20
文件頁(yè)數(shù): 17/136頁(yè)
文件大?。?/td> 2475K
代理商: ST72621J2B1
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I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 72. Typical VDD-VOH vs. VDD (high sink port)
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fCP, and TA unless otherwise specified.
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2 and the sum of IIO (I/
O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 73). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
3.5
4
4.5
5
5.5
6
Vdd (V)
V
DD
-V
OD
(V)
at
I
IO
=-2mA
0
0.05
0.1
0.15
0.2
0.25
3.5
4
4.5
5
5.5
6
Vdd (V)
V
DD
-V
OD
(V)
at
I
IO
=-5mA
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIH
Input High Level Voltage
0.7xVDD
VDD
V
VIL
Input Low Voltage
VSS
0.3xVDD
V
Vhys
Schmitt trigger voltage hysteresis 3)
400
mV
VOL
Output low level voltage 4)
VDD=5V
IIO=5mA
1
V
IIO=2mA
0.4
RON
Weak pull-up equivalent resistor 5)
VIN=VSS
80
160
280
k
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
6
30
1/fSFOSC
s
th(RSTL)in External reset pulse hold time
6)
10
s
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