- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98145 > ST72652C4T1/XXX (STMICROELECTRONICS) 8-BIT, MROM, MICROCONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號(hào)： | ST72652C4T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, TQFP-48 |
| 文件頁數(shù)： | 10/161頁 |
| 文件大?。?/td> | 2656K |
| 代理商： | ST72652C4T1/XXX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁
ST72651AR6
107/161
Doc ID 7215 Rev 4
IC SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.4 Functional Description (Master Mode)
Refer to the CR, SR1 and SR2 registers in Section
11.7.7. for the bit definitions.
By default the I2C interface operates in idle mode
(M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default idle mode to Master mode a
Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit causes the interface to
switch to Master mode (M/IDL bit set) and genera-
tes a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address byte, holding the SCL line low
(see Figure 64 Transfer sequencing EV1).
Then the slave address byte is sent to the SDA
line via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fi-
gure 64 Transfer sequencing EV2).
Next the master must enter Receiver or Transmit-
ter mode.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR regis-
ter via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register, hol-
ding the SCL line low (see Figure 64 Transfer se-
quencing EV3).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit clea-
red).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 64 Transfer sequencing
EV4).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gene-
rate the Stop condition. The interface goes auto-
matically back to idle mode (M/IDL bit cleared).
Error Case
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit. The AF bit is cleared
by reading the I2CSR2 register. However, if read
before the completion of the transmission, the AF
flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that
the SCL line is back at 0 before reading the SR2
register, or be able to correctly handle a second
interrupt during the 9th pulse of a transmitted
byte.
Note: In the event of this error, the SCL line is not
held low, however, the SDA line can remain low if
the last bits transmitted are all 0. While AF=1, the
SCL line may be held low due to SB or BTF flags
that are set at the same time. It is then necessary
to release both lines by software.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST7267R8T1L/XXX | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| ST7267C8T1/XXX | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| ST72774S9T1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72E734J6D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T774S9T1 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST7265X-EVAL/MS | 制造商:STMicroelectronics 功能描述:ST6 EVAL BD - Bulk |
| ST7265X-EVAL/PFD | 制造商:STMicroelectronics 功能描述:USB FLASH EVAL - Bulk |
| ST7266 | 制造商:6940 功能描述:ST7266 |
| ST7267C8T1L | 制造商:STMicroelectronics 功能描述: |
| ST72681/R12 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。