參數(shù)資料
型號： ST72652C4T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, ROHS COMPLIANT, TQFP-48
文件頁數(shù)： 110/161頁
文件大小： 2656K
代理商： ST72652C4T1/XXX
ST72651AR6
52/161
Doc ID 7215 Rev 4
10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity
Interrupt sensitivity, defined using the IS1[1:0] bits,
is applied to the ei0 interrupts (Port A):
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (fCPU output on
I/O port)
Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity
Interrupt sensitivity, defined using the IS2[1:0] bits,
is applied to the ei1 external interrupts (Port D):
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the CPEN bit. These
two bits are set and cleared by software
Caution:
– The ST7 core is not able to read or write in the
USB data buffer if the ST7265x is configured at 6
MHz in standalone mode.
– In USB mode, with fCPU ≤ 2 MHz, if the ST7 core
accesses the USB data buffer, this may prevent
the USB interface from accessing the buffer, re-
sulting in a USB buffer overrun error. This is be-
cause an access to memory lasts one cycle and
the USB has to send/receive at a fixed baud rate.
Note:
– A frequency change of the ST7 core does not af-
fect the frequency of the Data Transfer Coproc-
essor (DTC).
Bit 0 = CPEN Clock Prescaler Enable
This bit is set and cleared by software. It is used
with the CP[1:0] bits to configure the internal clock
frequency.
0: Default fCPU used (3 or 6 MHz)
1: fCPU determined by CP[1:0] bits
70
IS11
IS10
MCO
IS21
IS20
CP1
CP0 CPEN
IS11 IS10
External Interrupt Sensitivity
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
Rising and falling edge
IS21 IS20
External Interrupt Sensitivity
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
Rising and falling edge
Operating Mode
fCPU
CP1 CP0 CPEN
Stand-alone mode
(fOSC = 12 MHz)
3 MHz
x
0
6 MHz*
0
1
1.5 MHz
1
0
1
750 KHz
0
1
375 KHz
1
USB mode
(48 MHz PLL)
6 MHz
x
0
8 MHz
0
1
2 MHz
1
0
1
1 MHz
0
1
250 KHz
1
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