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參數(shù)資料
| 型號： | ST72652C4T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, TQFP-48 |
| 文件頁數(shù)： | 102/161頁 |
| 文件大?。?/td> | 2656K |
| 代理商： | ST72652C4T1/XXX |
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ST72651AR6
45/161
Doc ID 7215 Rev 4
9 I/O PORTS
9.1 INTRODUCTION
Important note:
Please note that the I/O port configurations of this
device differ from those of the other ST7 devices.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 31
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Mis-
cellaneous register.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically NANDed and inverted. For this rea-
son if one of the interrupt pins is tied low, it masks
the other ones.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 32).
When enabling/disabling an external interrupt by
changing port configuration (OR, DDR, control by
DTC), a spurious interrupt is generated if the pin
level is low and its edge sensitivity includes falling/
rising edge. This is due to the edge detector input
which is switched to '1' when the external interrupt
is disabled by port configuration.
To avoid this unwanted interrupt, a "safe" edge
sensitivity (rising edge for enabling and falling
edge for disabling) has to be selected before
changing the port configuration and configuring
the appropriate sensitivity again.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when
the
corresponding
interrupt
vector
is
fetched.
1
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